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Features
* Single-voltage Operation * * * * * * * * *
- 5V Read - 5V Reprogramming Fast Read Access Time - 45 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time - 1.5 seconds Word-by-word Programming - 10 s/Word Typical Hardware Data Protection Data Polling for End of Program Detection Small 10 x 14 mm VSOP Package Typical 10,000 Write Cycles
Description
The AT49F1024A is a 5-volt-only in-system Flash memory organized as 65,536 words by 16 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. To allow for simple in-system reprogrammability, the AT49F1024A does not require high-input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F1024A is performed by erasing a block of data (entire chip or main memory block) and then programming on a word-byword basis. The typical word programming time is a fast 10 s. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
1-megabit (64K x 16) 5-volt Only Flash Memory AT49F1024A
Pin Configurations
Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
A9 A10 A11 A12 A13 A14 A15 NC WE VCC NC CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSOP Top View Type 1 10 x 14 mm
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND
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The optional 8K word boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.
Block Diagram
VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O15 - I/O0 16 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING FFFFH MAIN MEMORY (56K WORDS) OPTIONAL BOOT BLOCK (8K WORDS) 2000H 1FFFH 0000H
Y DECODER ADDRESS INPUTS X DECODER
Device Operation
READ: The AT49F1024A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command (See Command Definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address (555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see main memory erase cycle waveforms. The main memory erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: Once the memory array is erased, the device is programmed (to a logic "0") on a word-by-word basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a four-bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The Data Polling feature may also be used to indicate the end of a program cycle.
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BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write-protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method and can be erased using either the Chip Erase or the Main Memory Block Erase command. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections), a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F1024A features Data Polling to indicate the end of a program or erase cycle. During a program cycle, an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data Polling may begin at any time during the program cycle. TOGGLE BIT: In addition to Data Polling, the AT49F1024A provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F1024A in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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Command Definition (in Hex)
Command Sequence Read Chip Erase Main Memory Erase Word Program Boot Block Lockout(3) Product ID Entry Product ID Exit
(4) (4)
Bus Cycles 1 6 6 4 6 3 3
1st Bus Cycle Addr Addr 555 555 555 555 555 555 Data DOUT AA AA AA AA AA AA
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
AAA(2) AAA AAA AAA AAA AAA
55 55 55 55 55 55
555 555 555 555 555 555
80 80 A0 80 90 F0
555 555 Addr 555
AA AA DIN AA
AAA AAA
55 55
555 555
10 30
AAA
55
555
40
Product ID Exit 1 xxx F0 Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex); A11 - A15 (Don't Care). 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. The 8K word boot sector has the address range 0000H to 1FFFH. 4. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC and AC Operating Range
AT49F1024A-45 Operating Temperature (Case) VCC Power Supply Com. 0C - 70C 5V 10%
Operating Modes
Mode Read Program
(2)
CE VIL VIL VIH X X X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware
X VIL VIH
High-Z
VIL
VIL
VIH
A1 - A15 = VIL, A9 = VH(3), A0 = VIL A1 - A15 = VIL, A9 = VH(3), A0 = VIH A0 = VIL, A1 - A15 = VIL A0 = VIH, A1 - A15 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
Notes:
1. 2. 3. 4. 5.
X can be VIL or VIH. Refer to AC programming waveforms. VH = 12.0V 0.5V. Manufacturer Code: 001FH, Device Code: 0087H. See details under "Software Product Identification Entry/Exit" on page 11.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH1 VOH2
(1)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA
Min
Max 10.0 10.0 100.0 1.0 50.0 0.8
Units A A A mA mA V V
2.0 IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 0.45
V V V
Note:
1. In the erase mode, ICC is 90 mA.
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AC Read Characteristics
AT49F1024A-45 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 45 45 30 25 Units ns ns ns ns ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
5.0V 1.8K OUTPUT PIN 1.3K 30 pF
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 50 50 0 40 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH
WE
CE Controlled
OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Word Programming Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 50 40 1.5 3 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
A0-A15
Main Memory or Chip Erase Cycle Waveforms
OE
CE
t WP t WPH
WE
t AS t AH
555
t DH
AAA 555 555 AAA 555
A0-A15
t DS
t EC
55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 NOTE 2 WORD 5
DATA
AA WORD 0
Notes:
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 10H. For a main memory erase, the data should be 30H.
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Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 6.
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 6.
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Boot Block Lockout Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 80 TO ADDRESS 555 LOAD DATA 90 TO ADDRESS 555
LOAD DATA AA TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA 55 TO ADDRESS AAA
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS LOAD DATA 40 TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE 1 second(2)
Notes:
LOAD DATA F0 TO ADDRESS 555
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
Address Format: A11 - A0 (Hex); A11 - A15 (Don't Care). 2. Boot Block Lockout feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
Address Format: A11 - A0 (Hex); A11 - A15 (Don't Care).
2. A1 - A15 = VIL.
Manufacturer Code is read for A0 = VIL. Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 0087H
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AT49F1024A Ordering Information
tACC (ns) 45 45 ICC (mA) Active 50 50 Standby 0.1 0.1 Ordering Code AT49F1024A-45VC AT49F1024A-45VL Lead Free Package 40V 40V Operation Range Commercial (0 to 70 C) Commercial (0 to 70 C)
Package Type 40V 40-lead, 10 mm x 14 mm, Thin Small Outline Package (VSOP)
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Packaging Information 40V - VSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 13.80 12.30 9.90 0.50 NOM - - 1.00 14.00 12.40 10.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 14.20 12.50 10.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. 40V REV. B
R
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3415B-FLASH-12/03

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